A 12-bit, 27.8-ps resolution, Anti-PVT variation multi-parallel sampling based coarse-fine TDC for LiDAR sensors

This paper presents a multi-parallel sampling based coarse-fine time-to-digital converter (TDC) with sub-gate delay resolution, large measurement range and high conversion rate for light detection and ranging (LiDAR) sensors. The fine-TDC is designed based on a voltage-controlled delay line (VCDL) but with multi-parallel sampling D flip-flop (DFF) groups to achieve a sub-gate delay resolution based on multi-phase interpolation. These DFF groups are triggered by several successively delayed sampling clocks that generated by a phase-locked loop (PLL) based multi-phase clock generator. The coarse-TDC composed of a coarse counter and a logical control circuit (LCC) is designed to enlarge the measurement range. The LCC is used to calibrate and guarantee the coarse counter neither over-counted nor under-counted. Since the delay of delay units in fine-TDC is also voltage-controlled by another PLL, the resolution of this proposed TDC is robust to process-voltage-temperature (PVT) variation. Besides, this proposed TDC architecture also has the property of dynamic element matching (DEM), which contributes to mitigate the impact of device mismatch and scramble the quantization noise. The post-layout simulations demonstrate a 12-bit, 27.8-ps time resolution, 0.86-LSB DNL, 0.92-LSB INL with 13.6-mW power consumption at 33.3-MS/s under a 1.8-V supply.