三元运算
物理
拓扑(电路)
计算机科学
电气工程
工程类
程序设计语言
作者
Yue Hao,Pengjun Wang,Yijiang Shi,Bo Chen,Gang Li,Xiangyu Li,Xiaojing Zha,Jianping Hu
出处
期刊:IEEE Transactions on Nanotechnology
[Institute of Electrical and Electronics Engineers]
日期:2023-01-01
卷期号:22: 713-721
标识
DOI:10.1109/tnano.2023.3323301
摘要
This paper proposes a novel dopingless ternary FET (DLT-FET) composed of the longitudinal metal-source/InAs-channel/InAs-drain structure for compact implementation of the ternary inverter. A single DLT-FET mixes two types of carrier transport mechanisms: 1) according to the concept of charge plasma, the Band-to-Band tunneling (BTBT) can occur at channel/drain interface by metal work function engineering; 2) Schottky Barrier tunneling (SBT) at the source/channel interface. The mechanism of the DLT-FET is verified with the help of TCAD tools. The simulation results revealed that both N/P-type DLT-FETs have a flat drain current characteristic around V G = 0.5 V DD , where the V G -independent I BTBT dominates the drain current. The stable third output voltage can be obtained through the voltage dividing, while both the I SBT and I BTBT generate the other voltage levels of 0 V and 1.0 V DD . Furthermore, the effects of a series of key device parameters on DLT-FETs and ternary inverter performance are evaluated. The ternary inverter can be implemented by simply replacing two transistors with N/P-type DLT-FETs in a conventional binary inverter and selecting appropriate device parameters for exhibiting comparable transfer characteristics.
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