期刊:IEEE Electron Device Letters [Institute of Electrical and Electronics Engineers] 日期:2018-04-01卷期号:39 (4): 618-621被引量:19
标识
DOI:10.1109/led.2018.2810075
摘要
We report the first investigation of the impacts of gate voltage sweep range V GS,range on the performance of negative capacitance (NC) transistors. As V GS,range is reduced, NC GeSn pFETs generally exhibit an increased hysteresis or a transition from non-hysteretic to hysteretic, and show a degradation of IDS. This is due to the reduction of the ratio of remnant polarization Pr to coercive field E c with the reduced voltage across the HZO. Interestingly, however, some NC devices show a negligible impact of V GS,range on hysteresis and IDS. The NC transistor demonstrates a stable hysteresis in 139-149 mV range and the improved SS and IDS over the control device, with a reduced V GS,range of 0.5 to -0.5 V. To obtain device performance independent of V GS,range , the ratio of Pr/Ec of the HZO needs to stabilize in a very small V GS,range .