Program charge interference and mitigation in vertically scaled single and multiple-channel 3D NAND flash memory

Vertical pitch scaling and channel splitting are under active research to increase bit density in 3D NAND flash memories. Here, we use 3D TCAD simulations to investigate the associated program charge interference from neighboring cells, both in single and multiple channel configurations. We find that interference-induced threshold voltage shifts increase significantly at scaled gate lengths and intergate spacings. In multiple channel configurations, additional sources of interference are present. We find the introduction of airgaps to be an essential mitigation strategy in these scaled devices and compare several possible configurations.