26.1 A 600ch 10b Source-Driver IC with a Charge-Modulation DAC Achieving 1-Horizontal Time of 1.5μs Suitable for 240Hz-Frame-Rate Mobile Displays

Source driver ICs (SD-ICs), tasked with digital-to-analog conversion (DAC) and signal drive into pixels, drastically impact image quality in displays. As the demand for higher spatial resolution to enhance visual realism grows, even in mobile displays, a larger number of source channels needs to be integrated into each SD-IC. The display's color depth is correlated with the data resolution of the DAC, which occupies the majority of the channel die area. Thus, boosting area efficiency (bit-resolution per area) in SD-IC design is vital for integrating more source channels on a single chip without compromising color depth. Also, high-frame-rate displays (beyond 60Hz) are gaining traction due to their smoother transitions, lower motion blur, and overall improved user experience. Nevertheless, the SD-IC's minimum available 1-horizontal (1-H) time, which is mainly constrained by the DAC time and the output buffer's slew rate, limits the increase in frame rate. Figure 26.1.1 (top left) illustrates prior attempts to improve area efficiency. DAC-embedded amplifiers [1, 2] able to interpolate between two voltages ($V_{L}$ and $V_{H}$) selected from a resistor-string can offer a moderate 1-H speed due to their single-stage design where sub-DAC and signal drive are merged. However, such interpolations are reliant on the small-signal transconductances $(G_{m})$ of the buffer amplifier, leading to linearity errors, particularly when $(V_{H} - V_{L})$ is substantial. Although switched-capacitor (SC) sub-DACs [3–5] have better area efficiency, they may not be ideal for higher frame rates due to time-consuming SC behaviors and the sequential 1-H process, termed ' drive-after-conversion'.