Process and Key Technology of Typical Advanced Packaging

ICs such as CPU, GPU, AP, and RFIC used today in high-performance computing, network communication, and smart mobile consumer products are continuously shrinking in size by following the Moore’s Law in advanced nodes to achieve enhanced performance, low power consumption, and high density in compact sizes. The requirement of high performance and high density pushes the rapid development of advanced packaging technologies away from traditional wire-bonding (WB) interconnect to flip-chip 2D array packaging, wafer-level packaging, 2.5D/3D system integration, SiP, etc. The current chapter describes the typical advanced packaging process flows and key technologies currently used in the IC package development and manufacturing. The individual topics focus on the important advanced packaging fundamentals including bumping technologies, wafer-level packaging, flip chip, fan-out packaging, TSV/3D, SiP system-in-packaging, etc., covering typical process flows, key technologies, and critical materials.