A review on numerical approach of reflow soldering process for copper pillar technology

This paper reviewed the state-of-art copper pillar technology in flip-chip packaging, driven by the semiconductor industry’s demands for thinner and faster data transmission. This technology with area array feature is a surface mount technology process used to form interconnection bonding between ball grid array chip and printed circuit board (PCB) by the reflow soldering process. The conversion of the flip-chip interconnection bump from the solder ball to the Cu pillar bump with the solder cap and the joint performance within the reflow oven are presented in this review. The simulation tools have recently facilitated the Cu pillar bump research during the PCB assembly process. Thus, this review focuses on the simulation modeling of the PCB assembly within a reflow oven using different numerical approaches. The thermal and air flow aspects of the reflow process are reviewed. The temperature distribution and the thermal stress condition of the PCB assembly within the reflow oven are predicted to understand better the fluid–structure interaction in the reflow oven. The considerations of air flow and thermal effects enhanced the study of fluid flow on the PCB assembly. Moreover, the Cu pillar technology challenges are also highlighted in this review. This review paper is expected to provide necessary information and direction to future researchers and industrial engineers when designing a brand-new surface-mounted component.