Lv32
388 积分 2024-01-03 加入
A comparative design study of continuous-time incremental sigma-delta ADC architectures
19小时前
已完结
Particle swarm optimization design of low-power multistage amplifier using gm/ID methodology
4个月前
已完结
A 14-Bit 500-MS/s Time-Interleaved ADC With Autocorrelation-Based Time Skew Calibration
7个月前
已完结
A 12-b 1-GS/s 31.5-mW Time-Interleaved SAR ADC With Analog HPF-Assisted Skew Calibration and Randomly Sampling Reference ADC
7个月前
已完结
A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS
8个月前
已完结
A 90GS/s 8b 667mw 64x interleaved SAR ADC in 32nm digital SOI CMOS,
8个月前
已完结
A 69.5mW 20GS/s 6b time-interleaved ADC with embedded time-to-digital calibration in 32nm CMOS SOI
8个月前
已完结
Convergence rates of the efficient global optimization algorithm for improving the design of analog circuits
8个月前
已完结
Infill sampling criteria for surrogate-based optimization with constraint handling
8个月前
已完结
An Integrated MaxFit Genetic Algorithm-SPICE Framework for 2-Stage Op-Amp Design Automation
9个月前
已完结
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