Lv71
5005 积分 2020-12-25 加入
A 1.06V 5Gb/s/pin 16Gb LPDDR4x DRAM Adopting Sense Amplifier with AC-Coupled Equalizer, Stacked Output Driver, and Clock MUX with Inverter-Based Transmission Gate for Mobile and Automotive Application
5小时前
已完结
Low-Complexity, Loop-Unrolled Decision-Feedback Equalizer for IM/DD System Using PAM Formats
1年前
已完结
Non-Pad-Based in Situ In-Operando CDM ESD Protection Using Internally Distributed Network
2年前
已完结
A 2-stage with 3-stack Comparator with Common Mode Range Extension Technique for Mobile DRAM Interface
3年前
已完结
A LPDDR4X Low Jitter Driver Scheme with High Speed
3年前
已完结
Design and Implementation of Fast Locking All-Digital Duty Cycle Corrector Circuit with Wide Range Input Frequency
3年前
已关闭
A 6-Locking Cycles All-Digital Duty Cycle Corrector with Synchronous Input Clock
3年前
已关闭
Fail-safe I/O to control RESET# pin of DDR3 SDRAM and achieve ultra-low system power
4年前
已完结
A 5.8-Gbps low-noise scalable low-voltage signaling serial link transmitter for MIPI M-PHY in 40-nm CMOS
4年前
已完结
0815水利工程一级学科简介
4年前
已驳回
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