Lv5
970 积分 2023-05-31 加入
High-speed baud-rate clock and data recovery
3小时前
已完结
A low‐cost digital calibration scheme for high‐resolution SAR ADC using Adaptive‐LMS
6个月前
已完结
Techniques for offset calibration in comparators
6个月前
已完结
A 12-bit 800MS/s pipelined A/D converter
6个月前
已完结
A Rail-to-Rail 12 MS/s 91.3 dB SNDR 94.1 dB DR Two-Step SAR ADC With Integrated Input Buffer Using Predictive Level-Shifting
1年前
已完结
A 103 fJ/b/dB, 10–26 Gb/s Receiver With a Dual Feedback Nested Loop CDR for Wide Bandwidth Jitter Tolerance Enhancement
1年前
已完结
Resistive Degeneration Linearization Dynamic Residue Amplifiers for Pipelined ADCs
1年前
已完结
Background LMS Calibration Algorithm Realization for SAR-ADC
1年前
已完结
A Quantization Noise Reduction Method for Delta-Sigma Fractional-N PLLs Using Cascaded Injection-Locked Oscillators
1年前
已完结
A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process
1年前
已完结
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