Lv7
4980 积分 2020-08-22 加入
A 7-bit 1.75-GS/s 6.9-fJ/conv.-step FoMw Loop-Unrolled Fully Asynchronous SAR ADC in 3-nm CMOS for a 224-Gb/s SerDes Receiver
11小时前
已完结
A 100-MHz bandwidth continuous-time sigma-delta ADC with 1 V supply in 28 nm CMOS
12小时前
已完结
A 500MS/s 12b single channel SAR-assisted pipelined ADC with two-stage open-loop dynamic amplifier
15小时前
已完结
A 25-GS/s 8-bit Current-Steering DAC With ADC-Based Duty-Cycle Detection in 40-nm CMOS
5天前
已完结
核心素养背景下英语阅读教学:问题、原则、目标与路径
1个月前
已完结
A Single-Channel 1-GS/s 7.48-ENOB Parallel Conversion Pipelined SAR ADC With a Varactor-Based Residue Amplifier
2个月前
已完结
An 11-bit 100-MS/s Pipelined-SAR ADC Reusing PVT-Stabilized Dynamic Comparator in 65-nm CMOS
2个月前
已完结
A Time-Interleaved SAR Assisted Pipeline ADC With a Bias-Enhanced Ring Amplifier
2个月前
已完结
An 11-bit 360-MS/s Pipelined SAR ADC With Feedback Factor Compensation Using a Dynamic Negative-C-Assisted Residue Amplifier
2个月前
已完结
A 13b 280MS/s Partial-Interleaving Pipelined-SAR ADC with Active Bias-Enhanced Ring Amplifier and Background Calibration
2个月前
已完结
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