Lv2
120 积分 2023-05-11 加入
7.9 An 8b 6-12GHz 0.18mW/GHz DC Modulated Ramp-Based Phase Interpolator in 65nm CMOS Process
26天前
已完结
7.4 A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and -74.2dBc Reference Spur
1个月前
已完结
A 2.4-GHz Multiphase Inductorless PLL With Coupled-Ring Oscillators and Time-Amplifying Phase–Frequency Detector for Low Phase Noise and Robust Locking Performances
1个月前
已完结
A 24.6-29.6GHz Hybrid Sub-Sampling PLL with Tri-State Integral Path Achieving 44fs Jitter and -254.8dB FOM in 28nm CMOS
5个月前
已完结
A 14 GHz Integer-N Sub-Sampling PLL With RMS-Jitter of 85.4 fs Occupying an Ultra Low Area of 0.0918 mm2
5个月前
已完结
A 4-to-16GHz Dual-Loop PLL Based on Current-Control RO and Calibration in a 6-nm FinFET
5个月前
已完结
A Fractional-N PLL for Multi-phase Clock Generation with Loop Bandwidth Enhancement
5个月前
已完结
Comments on "Analysis of the Bridged T-coil Circuit Using the Extra-Element Theorem
5个月前
已完结
A Sub-50-fsrms Jitter Fractional-N CPPLL Based on a Dual-DTC-Assisted Time-Amplifying Phase-Frequency Detector With Cascadable DTC Nonlinearity Compensation Algorithm
7个月前
已完结
An Improved Charge-Pump Design to Increase Tuning Range and Reduce Spurs in FMCW Radar Synthesizers
7个月前
已完结
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