Lv3
260 积分 2020-08-07 加入
A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR
4年前
已完结
A false-lock-free clock/data recovery pll for nrz data using adaptive phase frequency detector
4年前
已完结
A 4-Channel 1.25–10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control
4年前
已完结
Analysis and Minimization of Flicker Noise Up-Conversion in Voltage-Biased Oscillators
4年前
已完结
An equalizer-adaptation logic for a 25-Gb/s wireline receiver in 28-nm CMOS
4年前
已完结
A 4-Channel 10.3Gb/s Backplane Transceiver Macro with 35dB Equalizer and Sign-Based Zero-Forcing Adaptive Control
4年前
已完结
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