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Stephendo
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A 28-nm 18.7 TOPS/mm$^2$ 89.4-to-234.6 TOPS/W 8b Single-Finger eDRAM Compute-in-Memory Macro With Bit-Wise Sparsity Aware and Kernel-Wise Weight Update/Refresh
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eCIMC: A 603.1-TOPS/W eDRAM-Based Cryogenic In-Memory Computing Accelerator Supporting Boolean/Convolutional Operations
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Operation Scheme Optimizations to Achieve Ultrahigh Endurance (10$^{\text{10}}$) in Flash Memory
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Advanced 2T0C DRAM Technologies for Processing-in-Memory—Part II: Adaptive Layer-Wise Refresh Technique
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Advanced 2T0C DRAM Technologies for Processing-in-Memory—Part I: Vertical Transistor on Gate (VTG) DRAM Cell Structure
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Thermal Instability Compensation of Synaptic 3D Flash Memory-Based Hardware Neural Networks with Adaptive Read Bias
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Roadmap to neuromorphic computing with emerging technologies
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Process-Variation-Aware In-Memory Computation With Improved Linearity Using On-Chip Configurable Current-Steering Thermometric DAC
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First Experimental Demonstration of 3D-Stacked 2T0C DRAM Cells Based on Indium Tin Oxide Channel
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CIMFormer: A Systolic CIM-Array-Based Transformer Accelerator With Token-Pruning-Aware Attention Reformulating and Principal Possibility Gathering
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