Lv31
300 积分 2024-10-18 加入
32 nm logic technology featuring 2nd generation high-k + metal-gate transistors, enhanced channel strain and 0.171 μm2 SRAM cell size in a 291 Mb array
29天前
已完结
Piezoresistance Coefficients of (100) Silicon nMOSFETs Measured at Low and High ($\sim$1.5 GPa) Channel Stress
29天前
已完结
Strain Engineering in Si Split-Gate Trench Power MOSFETs by Partial Oxidation of Polysilicon Electrodes
1个月前
已完结
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