Uniaxial Strain Enhancement in SOI Technology for the Improvement of Channel and Exterior Resistances

Strain enhancement has been proven a viable enabler for transistor technology scaling. The implementation and performance of source/drain embedded SiGe (eSiGe) for devices on silicon-on-insulator (SOI) substrate are presented. With proper process controls to mitigate substrate challenges, significant PFET drive current improvement is obtained with SOI eSiGe. The impact of dimensional scaling factors on device enhancement is explored, and results demonstrate a good extendibility for eSiGe. It is also demonstrated that an optimized integration can lead to gate dielectric reliability improvement. The eSiGe contributions to the reductions of channel and exterior resistances are quantitatively depicted. Hole motility at high and low vertical fields has been calculated, and results show that the eSiGe enhancement on mobility changes little with vertical field variation.