Addition to “A Wideband 2.4-GHz Delta-Sigma Fractional- $N$ PLL With 1-Mb/s In-Loop Modulation”

[1] I. Bietti, E. Ternporitil, G. Albasini, and R. Castello, “An UMTS sigma delta fractional synthesizer with 200 kHz bandwidth and 128 dBc/Hz at 1 MHz using spurs compensation and linearization techniques,” in Proc. IEEE Custom Integrated Circuits Conf., Sep. 2003, pp. 463–466. [2] S. Pamarti, L. Jansson, and I. Galton, “A wideband 2.4-GHz delta-sigma fractional-N PLL with 1-Mb/s in-loop modulation,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 49–62, Jan. 2004.