Analysis and Design of Sigma-Delta ADCs for Automotive Control Systems

This paper presents a sigma-delta analog-to-digital converter (ADC) using discrete-time implementation dedicated to automotive control systems. The proposed ADC consists of a fourth-order sigma-delta modulator followed by a fifth-order cascaded integrator comb (CIC) decimator filter. The structure of the proposed modulator employs a cascaded integrator feed-forward (CIFF) topology. By using multi-bit quantizer, the modulator can apparently reduce quantization noise and make the loop more stable. Thanks to the input offset storage (IOS) technology and neutralization technology, the offset voltage of the comparator is sharply reduced by 35.5% and kick back noise is also eliminated. A random digital correction method is applied to make the feedback DAC insensitive to the mismatch of small-size capacitors and achieve better dynamic performance. The proposed ADC is implemented in a standard 0.18um CMOS process. Operating from a 1.8V supply, it achieves a peak spurious-free dynamic range (SFDR) of 105.8 dB and a peak signal-to-noise and distortion ratio (SNDR) of 93 dB at a conversion rate of 1 MS/s. The power consumption is 8.28 mW, which corresponds to a Walden figure-of-merit of 7.2 pJ/conv and a Schreier figure-of-merit of 155.8 dB.