A 5-bit High-Linearity, Binary-Recombination-Redundancy Sub-SAR ADC in 300MS/s, 14-bit Pipelined-SAR ADC

The paper presents a 5-bit high-linearity, binary-recombination-redundancy Sub-SAR ADC in 300MS/s, 14-bit Pipelined-SAR ADC in TSMC 28nm process. The highlight of the paper is the proposed high-linearity Sub-SAR ADC using binary recombination redundancy technique with high-speed SAR logic. In addition, the proposed high-speed SAR logic is energy-efficient. In this paper, the requirement proposed by C. Liu in 2015 is reconsidered, and after experimental simulation, a new requirement of the recombination capacitor cells removed from the MSB or sub-MSB is presented. It should satisfy the sum of a combination of the power-of-2 number of B, instead of the power-of-2 number of B. At 0.9V supply and 300MS/s, the proposed Sub-SAR ADC consumes 1.62mW, using a sampling capacitor array of 1.92pF at the input sine wave of ±0.3V. It achieves SNDR of 75.5dB and SNDR of 74dB at low and Nyquist frequency respectively, while the 3-stage pipelined-SAR ADC using the proposed Sub-SAR ADC finally achieves SNDR of 64.3dB, and SNDR of 64dB at low and Nyquist frequency, respectively. The whole ADC consumes 9.4mW, achieving FoMs of 166dB, or FoMw of 24.3fJ/conv.-step.