Optimal Placement of TDC Sensor for Enhanced Power Side-Channel Assessment on FPGAS

Power side-channel analysis (SCA) attack significantly threatens the security of cryptographic algorithms, which are otherwise computationally secure. Hence, evaluating the power SCA resiliency of a crypto implementation is critical before manufacturing. In this work, we utilize an FPGA-based framework to perform probeless power SCA leakage assessment, leveraging the prior works on the time-to-digital converter (TDC)-based voltage sensing. Most prior works use several TDC sensors spread throughout the FPGA fabric to sense the SCA leakage, which consumes a large area & is not a feasible solution when analyzing large IPs. Hence, in this work, we focus on the optimal placement of the TDC sensor on the fabric to minimize the total area. Specifically, this work performs a fundamental analysis of the impact of the power delivery network (PDN) on the TDC-based voltage sensing for power SCA leakage assessment of crypto IPs on an FPGA. Through spice-level PDN simulations & FPGA measurements, we obtain the optimal placement of the TDC to sense the maximum voltage fluctuations on the FPGA fabric. A dual-clock TDC with a shared clock tree is implemented to minimize the sensor area. The optimal placement of the dual-clock TDC circuit & a greedy gradient search heuristic to obtain the best TDC sampling point leads to $\sim 8 \times $ reduction in the sensor area compared to prior work using an Intel Stratix 10 FPGA. The proposed methodology is generic & can be applied to other TDC-based voltage sensing applications.