A 128 Gb/s, 11.2 mW Single-Ended PAM4 Linear TIA With 2.7 μArms Input Noise in 22 nm FinFET CMOS

We review the design trade-offs that exist in CMOS inverter-based shunt-feedback transimpedance amplifier (SF-TIA) when optimizing for energy efficiency. We analyze the performance of series and shunt inductive peaking techniques for bandwidth enhancement and identify the most effective one for low-power CMOS TIAs. As a design example, we present a 128-Gb/s single-ended linear transimpedance amplifier (TIA) intended for use in receivers for 400-G Ethernet optical modules and co-packaged optics. The inverter-based SF-TIA is implemented in a 22-nm fin field-effect transistor (FinFET) CMOS technology, supporting a data rate of 128-Gb/s PAM4 with a dc transimpedance gain of $59.3~{\mathrm{ dB}}{\cdot }\Omega $ while dissipating only 11.2 mW of power from a 0.8-V supply. It achieves a 3-dB transimpedance bandwidth of 45.5 GHz with a total integrated input referred noise current of $2.7~\mu \text{A}_{\text{rms}}$ . These results improve upon the state-of-the-art BiCMOS/CMOS linear TIAs, demonstrating the potential for building highly integrated, low-cost, high-sensitivity 100+G CMOS optical receivers using FinFET CMOS process technology.