Prototype development of a three-stage, high-precision, low-jitter, wide-range digital delay generator fully utilizing on-chip resources

This paper introduces the design and implementation of a prototype Digital Delay Generator (DDG) characterized by high precision, low jitter, and a wide delay range, fully realized within a Field Programmable Gate Array (FPGA). The DDG’s architecture is based on an innovative combination of an embedded time-to-digital converter (TDC) and Multi-stage Time Interpolation (MTI) delay logic. The paper explores the factors influencing delay jitter during external trigger mode and carefully selects the optimal design approach for each element. The embedded TDC, which undergoes automatic calibration, accurately measures the time difference between the arrival of an external trigger and the FPGA’s internal clock signal. When paired with the MTI delay logic, this allows for highly precise control over delay durations. A key aspect of this design is its sole dependence on the FPGA’s built-in resources, ensuring simplicity in implementation and adaptability to various applications. Evaluation of the prototype has shown promising results, demonstrating a delay resolution as fine as 20 ps and maintaining a low jitter of 105 ps peak-to-peak (20 ps rms) when operated in the externally triggered mode.