Cause of Etch Pits during the High Speed Plasma Etching of Silicon Carbide and an Approach to Reduce their Size

To reduce the on-resistance in vertical power transistors, backside thinning is required after device processing. However, it is difficult to thin silicon carbide (SiC) wafers with a high removal rate by conventional mechanical processing because their hardness and brittleness cause cracks and chips during thinning. Therefore, the authors have attempted to thin SiC wafers using plasma chemical vaporization machining (PCVM), which is plasma etching using high-pressure plasma. PCVM has a high removal rate because of the high radical density in the high-pressure plasma, and it does not form a damaged layer on the processed surface because of the low ion energy. The authors have already achieved a very high removal rate of 15.6 μm/min by PCVM. However, many etch pits were generated on the wafer during PCVM in these high-speed machining conditions. Therefore, this study, using molten potassium hydroxide (KOH) etching, investigated the cause of such etch pits and found that they may stem from threading screw dislocation in the wafers. In addition, this research considered a process for reducing an etch pit size and succeeded in doing so by controlling wafer temperature.