CMOS‐Integrated Ternary Content Addressable Memory using Nanocavity CBRAMs for High Sensing Margin

Abstract The development of data‐intensive computing methods imposes a significant load on the hardware, requiring progress toward a memory‐centric paradigm. Within this context, ternary content‐addressable memory (TCAM) can become an essential platform for high‐speed in‐memory matching applications of large data vectors. Compared to traditional static random‐access memory (SRAM) designs, TCAM technology using non‐volatile resistive memories (RRAMs) in two‐transistor‐two‐resistor (2T2R) configurations presents a cost‐efficient alternative. However, the limited sensing margin between the match and mismatch states in RRAM structures hinders the potential of using memory‐based TCAMs for large‐scale architectures. Therefore, this study proposes a practical device engineering method to improve the switching response of conductive‐bridge memories (CBRAMs) integrated with existing complementary metal‐oxide‐semiconductor (CMOS) transistor technology. Importantly, this work demonstrates a significant improvement in memory window reaching 1.87 × 10 7 by incorporating nanocavity arrays and modifying electrode geometry. Consequently, TCAM cells using nanocavity‐enhanced CBRAM devices can exhibit a considerable increase in resistance ratio up to 6.17 × 10 5 , thereby closely approximating the sensing metrics observed in SRAM‐based TCAMs. The improved sensing capability facilitates the parallel querying of extensive data sets. TCAM array simulations using experimentally verified device models indicate a substantial sensing margin of 65× enabling a parallel search of 2048 bits.