光掩模
光学接近校正
计算机科学
薄脆饼
集成电路布局
水准点(测量)
制作
集成电路
平版印刷术
参数统计
IC布局编辑器
一致性(知识库)
人工智能
过程(计算)
工程制图
电路提取
材料科学
工程类
抵抗
等效电路
数学
纳米技术
光电子学
电气工程
电压
病理
操作系统
统计
替代医学
地理
医学
大地测量学
图层(电子)
作者
Hao-Chiang Shao,Chao-Yi Peng,Jun-Rei Wu,Chia‐Wen Lin,Shao-Yun Fang,Pin-Yian Tsai,Yan-Hsiu Liu
标识
DOI:10.1109/tcad.2020.3015469
摘要
We propose a deep learning-based data-driven framework consisting of two convolutional neural networks: 1) LithoNet that predicts the shape deformations on a circuit due to IC fabrication and 2) OPCNet that suggests IC layout corrections to compensate for such shape deformations. By learning the shape correspondences between pairs of layout design patterns and their scanning electron microscope (SEM) images of the product wafer thereof, given an IC layout pattern, LithoNet can mimic the fabrication process to predict its fabricated circuit shape. Furthermore, LithoNet can take the wafer fabrication parameters as a latent vector to model the parametric product variations that can be inspected on SEM images. Besides, traditional optical proximity correction (OPC) methods used to suggest a correction on a lithographic photomask is computationally expensive. Our proposed OPCNet mimics the OPC procedure and efficiently generates a corrected photomask by collaborating with LithoNet to examine if the shape of a fabricated circuit optimally matches its original layout design. As a result, the proposed LithoNet-OPCNet framework can not only predict the shape of a fabricated IC from its layout pattern but also suggests a layout correction according to the consistency between the predicted shape and the given layout. Experimental results with several benchmark layout patterns demonstrate the effectiveness of the proposed method.
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