A 64-Gb/s 0.33-pJ/bit PAM4 Receiver Analog Front-End with a Single-Stage Triple-Peaking CTLE Achieving 22.5-dB Boost in 40-nm CMOS Process

This paper presents a PAM4 receiver analog-front end (AFE) circuit. Our proposed single-stage triple-peaking continuous-time linear equalizer (CTLE) stage with current reuse technique is adopted to achieve low, middle and high frequency peaking concurrently. Thus, only one-stage CTLE is sufficient to achieve an over-20-dB boost at Nyquist frequency to save power. A variable-gain amplifier (VGA) is used to reduce the DC-gain variation at different CTLE equalization settings. Fabricated in a 40-nm CMOS process, our prototype AFE achieves 64-Gb/s data rate, 22.5-dB maximum peaking boost at 16-GHz, and an energy efficiency of 0.33 pJ/bit at 64-Gb/s data rate. It also features low, middle and high frequency peaking so that it can compensate a 12-dB channel loss at Nyquist frequency of 16-GHz.