接触电阻
材料科学
欧姆接触
CMOS芯片
电气工程
物理
拓扑(电路)
纳米技术
光电子学
工程类
图层(电子)
作者
Ang‐Sheng Chou,Yu‐Tung Lin,Yuxuan Lin,Ching-Hao Hsu,Ming‐Yang Li,San‐Lin Liew,Sui-An Chou,Hung‐Yu Chen,Hsin‐Yuan Chiu,Po‐Hsun Ho,Ming-Chun Hsu,Yu-Wei Hsu,Ning Yang,Wei-Yen Woon,Szuya Sandy Liao,Duen‐Huei Hou,Chao-Hsin Chien,Wen‐Hao Chang,Iuliana Radu,Chih‐I Wu,H.‐S. Philip Wong,Han Wang
标识
DOI:10.1109/iedm45625.2022.10019491
摘要
Low resistance contact technology for 2D semiconductors is a key bottleneck for the practical application of 2D channel materials at advanced logic nodes. This work presents a novel Sb-Pt modulated contact technology which can alleviate the Fermi-level pinning effect and mediate the band alignment at the metal-2D semiconductor interface, leading to exceptional ohmic contacts for both p-type and n-type WSe 2 FETs (p/n FET). WSe 2 FETs with different Sb/Pt contact compositions, in combination with new oxide-based encapsulation/doping technologies, exhibits record low pFET contact resistance of $0.75 \mathrm{k}\Omega \bullet \mu \mathrm{m}$ among all reported monolayer (1L) 2D pFETs. The nFET contact resistance of $1.8 \mathrm{k}\Omega \bullet \mu \mathrm{m}$ is also the lowest among 1L WSe 2 nFETs. Both 1L WSe 2 pFET and nFET demonstrated remarkable on-state p/n current $\sim 150 \mu \mathrm{A}/ \mu \mathrm{m}$ at $\vert \mathrm{V}_{D} \vert =1\mathrm{V}$, indicating the potential of WSe 2 for CMOS applications. A new version of the semi-automated dry transfer process for chemical vapor deposition (CVD) WSe 2 was also developed utilizing a novel Bi/PMMA/TRT support stack, offering low defect wrinkle-free WSe 2 transfer at wafer-scale.
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