Preface: Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 4: New Materials, Processes, and Equipment

The editors (of North Carolina State U., Qualcomm MEMS Technologies, and Mattson Technology Inc. in the United States; Tokyo Institute of Technology in Japan; Institute of Microelectronics in Singapore; and NXP Semiconductors Research in the Netherlands) present 53 papers from the international symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment 4 (CMOS stands for complementary metal-oxide semiconductor), held in May 2008 as part of the 213th Meeting of the Electrochemical Society. Following the keynote on the semiconductor industry's Nanoelectronics Research Initiative, opening papers discuss dopant activation and diffusion and include studies of novel flash-lamp and laser annealing approaches. The next section covers gate-stack engineering, with most papers focusing on atomic-layer deposition-grown high-k/metal gate stacks, although several address the recent implementation of high-k/metal gate CMOS in volume manufacturing. Channel engineering is addressed next in chapters that discuss the use of strain; the incorporation of new materials such as silicon-germanium, germanium, and III-V compounds; and new device configurations based on fin-shaped field effect transistors and nanowires. The next set of papers explores contacts, focusing on new approaches and materials that can help overcome the challenge of parasitic resistance in highly scaled CMOS. The remaining papers discuss novel processes for advanced memory technologies.