A 12.8–15.0-GHz Low-Jitter Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation

This article presents a low-jitter, low-fractional spur fractional- $N$ subsampling phase-locked loop (SSPLL) that generates an output frequency, $f_{\mathrm {OUT}}$ , that ranges from 12.8 to 15.0 GHz. Conventionally, fractional- $N$ SSPLLs remove the quantization error (Q-error) of the delta–sigma modulator ( $\Delta \Sigma \text{M}$ ) before the sample-and-hold (SH) circuit using a digital-to-time converter (DTC). As a result, the in-band noise of those SSPLLs is saturated by the jitter of the DTC, and the overall rms jitter is increased. However, the proposed SSPLL cancels the Q-error after the SH using a digital-to-analog converter (DAC). This approach significantly suppresses the jitter of the DAC by the gain of the SH, $K_{\mathrm {SH}}$ , resulting in a much lower rms jitter. To implement the proposed Q-error cancellation, this work introduces two key techniques: 1) dual-clock-phase sampling (DCP sampling) that maintains a consistently high $K_{\mathrm {SH}}$ and 2) second-order curve-fitting digital predistortion (SCF-DPD) that enables the DAC to cancel the Q-error more precisely. The proposed fractional- $N$ SSPLL was fabricated in a 65-nm CMOS technology, and the total power consumption was 7.3 mW when a 14-GHz $f_{\mathrm {OUT}}$ was generated using a reference frequency of 100 MHz. The measured rms jitter and the level of fractional spurs were 104 fs and −58 dBc, respectively.