抖动
占空比
滤波器(信号处理)
电压
循环(图论)
CMOS芯片
噪音(视频)
材料科学
低通滤波器
控制理论(社会学)
物理
电气工程
数学
计算机科学
光电子学
工程类
控制(管理)
组合数学
人工智能
图像(数学)
作者
Eun‐Young Jung,Won Young Lee
标识
DOI:10.1016/j.aeue.2023.154568
摘要
In this paper, a duty cycle corrector (DCC) with a dual loop low pass filter (DLLPF) has been proposed to improve correction time and noise characteristics. It shows that the correction time is 4.25 times faster and the fluctuation is 7.86 times lower compared to a conventional DCC with a typical low pass filter. The proposed DCC has been fabricated in a 0.18-μm CMOS technology with a supply voltage of 1.8 V within area of 0.03 mm2. The experimental results show that the operation range is from 800 MHz to 1.6 GHz for input duty cycle variation within 25 % and 75 %. At the 1.6 GHz operating frequency, the measured root-mean-square and peak-to-peak jitters are 1.66 ps and 12.69 ps, respectively.
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