Hybrid CMOS-PCM Ternary Logic for Digital Circuit Applications

This paper presents hybrid design of a Ternary Inverter (TI) circuit by integrating an Ovonic-Threshold-Switching (OTS) based Phase-Change-Memory (PCM) cell between Complementary-Metal-Oxide-Semiconductor (CMOS) transistors. Volatile OTS behaviour of the PCM structure helps to generate the ternary state. Reliability of the proposed TI design has been demonstrated through the Monte-Carlo simulations in Cadence-Spectre simulator incorporating both Process and Mismatch variability at all corners. The proposed inverter cell consumes 10.44 $\mu$ W power and 1.47 ns delay on UMC-180 nm technology node. Moreover to demonstrate the scaling potential, we have simulated the proposed inverter at various technology nodes i.e 180/90/65/28 nm. At advanced feature sizes, power and delay are improved by significant amount. For benchmarking, we have compared the proposed TI design with various state-of-the-art hybrid structures. Furthermore, to demonstrate potential applications, we designed and simulated ternary universal logic gates i.e NAND/NOR. Benefits of the proposed TI in circuit applications are shown through a Ternary Multiplier (TMUL) arithmetic circuit implementation. Finally, a Ternary-Static-Random-Access-Memory (TSRAM) is proposed with two back-to-back connected CMOS-PCM TIs with three bit storing capability.