Lithography reticle scheduling in semiconductor manufacturing

The lithography process in semiconductor dynamic random-access memory (DRAM) fabrication plants (fabs) is usually a major bottleneck, and reticle scheduling is complicated by process-specific constraints such as diversity of the product mix and rapidly changing deadlines. This study proposes a three-phase scheduling framework to solve the multi-objective reticle scheduling problem, reducing capacity loss, maintaining line balance and meeting customer demand. The genetic algorithm (GA) and the technique for order preference by similarity to ideal solution (TOPSIS) are used to optimize the scheduling with a trade-off among the multiple objectives. This study tests the proposed framework based on a real semiconductor DRAM (fab) in Taiwan, which has two unrelated parallel machines in its lithography process. The study finds that the proposed framework results in better scheduling reports, reduced computation times and improvements in the overall performance of lithography equipment.