Sub-10-nm-thick SiN nanopore membranes fabricated using the SiO2 sacrificial layer process

In our previous studies, ultrathin SiN membranes down to 3 nm in thickness were fabricated using the poly-Si sacrificial layer process, and nanopores were formed in those membranes. The region of the SiN membrane fabricated using this process was small, and the poly-Si sacrificial layer remained throughout the other region. On the other hand, to reduce the noise of the current through the nanopore, it is preferable to reduce the capacitance of the nanopore chip by replacing the poly-Si layer with an insulator with low permittivity, such as SiO2. Thus, in this study, the fabrication of SiN membranes with thicknesses of 3–7 nm using the SiO2 sacrificial layer process was examined. SiN membranes with thicknesses of less than 5 nm could not be formed when the thickness of the top SiN layer deposited onto the sacrificial layer was 100 nm. In contrast, SiN membranes down to 3.07 nm in thickness could be formed when the top SiN layer was 40 nm in thickness. This is thought to be due to the difference in membrane stress. Nanopores were then fabricated in the membranes via dielectric breakdown. The current noise of the nanopore membranes was approximately 3/5 that of membranes fabricated using the poly-Si sacrificial layer process. Last, ionic current blockades were measured when poly(dT)60 passed through the nanopores, and the effective thickness of the nanopores was estimated based on those current-blockade values. The effective thickness was approximately 4.8 nm when the deposited thickness of the SiN membrane was 6.03 nm. On the other hand, the effective thickness and the deposited thickness were almost the same when the deposited thickness was 3.07 nm. This suggests it became difficult to form a shape in which the thickness of the nanopore edge was thinner than the deposited membrane thickness as the deposited thickness decreased.