P‐13.9: Study of AMOLED Vertical‐Crosstalk mechanism and improvement

The Simulation Model of Back Plane Circuit Vertical Crosstalk (BP‐VC) of AM‐OLED displays was established according to the experimental VC test method in this paper. The impact of the Pixel Storage capacitance (C st ) and the Parasitic Capacitance had been studied. Pixel with good simulated VC had been optimized by increasing C st and decreasing the parasitic capacitance of gate electrode of driving TFT (N1 node) and Gate line (Cap2), thus reaching the achievement that BP‐VC decreases from 1.54% to 0.76% in 6.5 inch FHD OLED Display.