A 2-GS/s 200-MHz BW Oversampling Continuous-Time Pipeline ADC with Adaptive Digital Filter in 28nm

An oversampling continuous-time (CT) pipeline ADC with RC delay line and inherent anti-aliasing is presented, avoiding aliasing from switched-capacitor circuit, high power consumption of buffer and excess anti-aliasing filter. The digital reconstruction filter is implemented using least mean square (LMS) engine, tracing the deviation of analog filter due to PVT variations and chip production. The analog segment is fabricated in 28nm CMOS, one CT pipeline stage clocked at 4GHz followed by a 13-bit 4× time-interleaved pipeline-SAR ADC clocked at 2GHz as the backend ADC. A Simulink model is established, and the 84dB SNDR @-2dBFS of 14-bit design specifications proves the rationality of the CT architecture and applicability of LMS engine in two pipeline stages clocked at respective frequencies.