Breakthrough Design Technology Co-optimization using BSPDN and Standard Cell Variants for Maximizing Block-level PPA

The challenge in designing a modern process beyond 3nm is that scaling is no longer based on incremental change purely at the process level [1]. In facing end of Moore’s Law, we need to find out novel innovative ideas to reduce the gap between reality and Moore’s Law trend as shown Fig. 1. In this paper, we introduce breakthrough design technology co-optimization knobs to maximize block-level PPA for advanced CMOS technology. Through these knobs, we improve Fmax +3.6% and block area -14.8% with back-side power delivery network (BSPDN). Furthermore, through the standard cell variants, block area is reduced up to -2.4% and block performance is improved about +1.6%