Improved Dynamic Comparator With Adaptive Delay Line for the Latch Conduction and Regenerative Feedback Assisted FIA

This article presents a low-noise energy-efficient comparator design. Firstly, by using an adaptive delay line based on the differential voltage at the output of the pre-amplifier, the delayed clock turns on the latch stage after the pre-amplifier stage where the delay is automatically changed depending on the input voltage level. Secondly, a regenerative feedback assisted Dynamic Floating Inverter Amplifier (FIA) is used to increase integration speed and gain. For Successive-approximation-register (SAR) ADCs where each bit is determined sequentially and the input voltage level differs in each cycle, the comparator resolves small analog inputs up to twice per conversion theoretically. The time taken by the proposed comparator to resolve analog input into digital output (called CLK-OUT delay) only increases in the small signal voltage range (near its input-referred noise level) which has less impact on SAR ADCs sample rate. The proposed comparator in 28 nm process technology achieves 66.37-uV input-referred noise while consuming approximately 780 fJ per comparison under a 0.9-V supply. This represents greater than 20-time energy efficiency boost compared to the previous comparator with a dynamic floating inverter pre-amplifier.