Gate Bias Effects on Hydrogen-Terminated Polycrystalline Diamond FETs

符号 域代数上的 数学 算术 纯数学
作者
Hongyue Wang,Yuebo Liu,Lei Ge,Mingsheng Xu,Yijun Shi,Zongqi Cai,Kai Huang,Zhiyuan He,Yan Peng,Xiwei Wang,Jinyan Wang
出处
期刊:IEEE Transactions on Electron Devices [Institute of Electrical and Electronics Engineers]
卷期号:71 (1): 406-411
标识
DOI:10.1109/ted.2023.3336633
摘要

In this article, gate bias ( $\textit{V}_{\text{GS},\text{stress}}\text{)}$ effects on the hydrogen (H)-terminated polycrystalline diamond field effect transistors (FETs) are investigated. A 7-to 8-nm AlO $_{\text{x}}$ interface layer is found between the Al metal and polycrystalline diamond by electrical and microstructure characterization. The threshold voltage ( $\textit{V}_{\text{TH}}\text{)}$ and ON-resistance ( $\textit{R}_{\text{on}}\text{)}$ exhibit different changing trends under varying $\textit{V}_{\text{GS},\text{stress}}$ . Specifically, a bidirectional shift of $\textit{V}_{\text{TH}}$ is observed during gate bias stress. To explain the distinct behavior of $\textit{V}_{\text{TH}}$ shift and $\textit{R}_{\text{ON}}$ change occurring under gate bias, holes trapping by defects, H-motion, and surface leakage electron trapping models are proposed. Under negative gate bias, holes in 2-D hole gas channel are captured by the interface states and/or defects in the AlO $_{\text{x}}$ layer, resulting in a negative shift of V $_{\text{TH}}$ . Simultaneously, H-motion in the AlOx layer under gate bias leads to the generation of negative charges. Additionally, electrons in the surface leakage path are trapped by defects on the diamond surface in the access region, leading to decreased access region resistance. For a harsh gate bias, a high density of new defects is generated, and a defect density changes from 4.9 $\times$ 10 $^{\text{21}}$ ev $^{-\text{1}}$ cm $^{-\text{3}}$ for the fresh device to 5.1 $\times$ 10 $^{\text{23}}$ ev $^{-\text{1}}$ cm $^{-\text{3}}$ for the device after gate bias ( $\textit{V}_{\text{GS},\text{stress}}$ $=$ $-$ 4 V) which is characterized by using the low-frequency noise measurements. These findings highlight the importance of surface passivation and high-quality gate dielectric in suppressing charging effects and new defect generation in H-terminated polycrystalline diamond FETs, ultimately contributing to device stability.
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