神经形态工程学
冯·诺依曼建筑
CMOS芯片
计算机科学
计算机体系结构
电阻器
记忆电阻器
计算
非常规计算
电子工程
人工神经网络
人工智能
工程类
电气工程
分布式计算
算法
操作系统
电压
作者
M. Darwish,Vehbi Calayir,Lawrence T. Pileggi,Jeffrey A. Weldon
标识
DOI:10.1109/tnano.2016.2525039
摘要
Brain-inspired or neuromorphic computing has been proposed as a method to overcome the limitations of the von-Neumann architecture. Neuromorphic computing relies on an array of neurons interconnected locally through synapses to perform computing functions such as pattern recognition and image processing. Neuromorphic computing with CMOS-based circuits has limited utility due to the relatively large area required by neurons and synapses, limiting the size of the neuromorphic network implementable on chip. In this paper, we present a novel ultracompact graphene variable resistor that can be used to implement both neurons and synapses. To illustrate the functionality of the proposed devices, we present a 3-bit digitally controlled synapse prototype that occupies 3 μm × 9.3 μm. The proposed devices pave the way for high-performance large neuromorphic networks that can be integrated with CMOS to augment its functionality or for beyond CMOS computation.
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