Dummy Gate Footing Problems in Scaling Down of FinFET Structures

The use of sacrificial dummy gate has been a standard process for HKMG in planar CMOS and subsequent FinFET technologies. However, the scaling down of FinFET design has led to a significant increase for the aspect ratio of gate structure. The profile of the dummy gate is of great importance for device performance and control of the dummy gate footing has become a prominent challenge. Here we studied dummy gate footing during high aspect ratio gate etch and its influence on device performance using virtual fabrication methods. At 7/5 nm FinFET technology node (as defined in IRDS 2018), the channel capacitance of the HKMG, which contributes to the AC performance, is showing to have percentage level differences respect to the existence/absence of dummy gate footing. Other problems posed by the dummy gate footing for subsequent procedures are also discussed. Figure 1