Build fast, trade fast: FPGA-based high-frequency trading using high-level synthesis

High-Frequency Trading (HFT) systems require extremely low latency in response to market updates. This motivates the use of Field-Programmable Gate Arrays (FPGAs) to accelerate different system components such as the network stack, financial protocol parsing, order book handling and even custom trading algorithms. However, the long cycle of developing and verifying FPGA designs makes it challenging for HFT software developers to deploy such highly-dynamic systems, especially with their limited hardware design expertise. We present a complete highly-optimized infrastructure that implements low-latency system components in C++ using High-Level Synthesis (HLS). We also develop a framework that enables HFT algorithm developers to implement their trading algorithms in a high-level programming language and rapidly integrate it to the rest of the system. We implemented our HLS-based system on a Xilinx Kintex Ultrascale FPGA running at 156 MHz. Our on-board measurements show an end-to-end round-trip latency less than 870ns, which is comparable to that achieved by prior RTL-based implementations but requires reduced system development time and effort.