静电放电
计算机辅助设计
集成电路设计
设计流量
电路设计
工艺CAD
炸薯条
电子设计自动化
工程类
电子工程
物理设计
计算机科学
嵌入式系统
电气工程
电压
工程制图
作者
Zijin Pan,Weiquan Hao,Xunyu Li,Runyu Miao,Albert Wang
标识
DOI:10.23919/eos/esd58195.2023.10287665
摘要
On-chip ESD protection design will be more and more challenging for emerging IC technologies and complex chips. This paper reviews a few proven CAD-based on-chip ESD protection design methodologies, including TCAD-based mixed-mode ESD protection design method, 3D TCAD ESD simulation to address the ESD layout design sensitivity, multi-stimuli ESD simulation technique, ECAD-based circuit-level ESD protection design approach, ESD-IC co-design technique, and novel CAD algorithm and flow for full-chip ESD protection circuit physical design verification. Future ESD protection design perspectives are highlighted.
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