Research on the Functional Failure of Large Scale Chips Caused by Recoverable Latch up

With the rapid development of advanced semiconductor technology and large size package, more and more latch up problems are found to be related to package structure, circuit design, wafer process and stress conditions, instead of being triggered by electrical stress only. It is also noted that some functional failures caused by recoverable latch up are increasing. Usually latch up failure is caused by application voltage or current that triggers the parasitic bipolar junction transistor in the CMOS circuit, forming a low resistance and high current channel, and thus inducing device damage. However, the failure of the mentioned recoverable latch up is difficult to catch and analyze. Therefore, a function failure caused by recoverable latch up is studied in this paper. By building a dynamic EMMI environment based on automatic test equipment and EMMI, the parasitic leakage channel of the failed chip during operation is successfully identified. The failure mechanism of functional failure is confirmed by following reliability test and TCAD simulation, which is helpful on understanding and improving the device reliability.