DTCO of sequential and monolithic CFET SRAM

Sequential and monolithic complementary FET (CFET) have become the most attractive device options for continuing the area scaling of SRAM beyond 5-Å-compatible technology (A5). The stacked architecture of CFET has eradicated the need for PMOS and NMOS (PN) separation and thereby enables cell height scaling of 40% compared to 10-Å-compatible technology (A10) forksheet (FS) SRAM. However, the routing becomes challenging with aggressive area scaling. This work proposes interconnect designs for A5 CFET SRAM and explores process integration options for corresponding solutions.