寄生提取
兴奋剂
材料科学
纳米技术
逻辑门
纳米片
和大门
扩散
阈下传导
纳米线
电气工程
光电子学
电压
电子工程
工程物理
计算机科学
工程类
晶体管
物理
热力学
作者
Ray Duffy,Fintan Meaney,Emmanuele Galluccio
出处
期刊:ECS transactions
[The Electrochemical Society]
日期:2020-04-24
卷期号:97 (3): 63-74
被引量:3
标识
DOI:10.1149/09703.0063ecst
摘要
The IEEE International Roadmap for Devices and Systems (IRDS) for More Moore devices summarises the Logic Device state of play very effectively; the FinFET is the key device architecture that could enable logic device scaling until 2025. Increasing fin height while reducing number of fins at unit footprint area is an effective solution to improve performance. It is forecasted that the parasitics will remain as a dominant term in the performance of critical paths. For reduced supply voltage, a transition to gate-all-around (GAA) structures such as lateral nanowires or nanosheets will be necessary to improve electrostatics. Lateral GAA structure would eventually evolve in to the vertical GAA structure to gain back the performance loss due to increasing parasitics at tighter pitches. In this paper we will consider doping techniques based on ion implant, solid-source in-diffusion, liquid-source in-diffusion, and gas-source in-diffusion for these device technologies.
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