Latency Minimal Scheduling with Maximum Instruction Parallelism

High Level Synthesis (HLS) is to synthesize circuits from algorithmic level descriptions. There is a strong need to deploy HLS in high performance computing for data center and edge computing. In this paper, we propose a new scheduling algorithm based on an instruction-level Dependency Graph (DG) for latency minimization. Unlike existing scheduling algorithms assuming a sequential execution order of Basic Blocks (BBs), we can identify instruction parallelism across BBs and schedule them parallelly for smaller circuit latency. Our test results show that we can significantly improve the circuit latency when compared with the state-of-the-art SDC-based LegUp and even outperform PandA with sophisticated code motion heuristics by 8% on average.