A 14-bit 4-MS/s VCO-Based SAR ADC With Deep Metastability Facilitated Mismatch Calibration

This article presents a 14-bit 4-MS/s voltage-controlled oscillator (VCO)-based successive approximation register (SAR) analog-to-digital converter (ADC), where the metastability of the VCO-based comparator is exploited for the background calibration of mismatch errors. A closed-form behavioral analysis of VCO-based comparators has been studied in the presence of noise, showing that the metastability is of unique characteristics as compared to voltage-domain comparators, and the metastability can be evaluated quantitatively by observing the number of oscillation cycles. Deep metastability (DM) indicates a condition where the signal and noise are sufficiently small as compared to mismatch errors, based on which an analog background calibration technique is proposed. A decision stabilizer is employed to deal with the limit-cycle oscillations (LCOs). Fabricated in a 40-nm CMOS technology, the ADC prototype exhibits peak signal-to-noise-and-distortion ratio (SNDR) of 78.7 dB and >93-dB spurious-free dynamic range (SFDR) across nine samples. At 2 and 4 MS/s, the ADC, including calibration logic, consumes only 94 and 157 μW from a 1.1-V supply, achieving a peak Schreier figure of merit (FoM) of 179.0 and 177.7 dB, respectively.