Functional Verification of Clock Domain Crossing in Register Transfer Level

Numerous million-transistor systems running with multiple asynchronous clocks at frequency as high as multiple gigahertz have been made possible by diminishing component geometries and more complicated designs. Multiple interfaces are available on SoC systems, some of which employ standards with wildly divergent clock frequencies. Many contemporary serial interfaces are by nature asynchronous with the rest of the chip. To address the issue of clock skew across big processors, significant SoC sub-blocks are increasingly being designed to operate on separate clocks. Partition-based implementation and verification have typically been the primary emphasis of design approaches. These divisions are frequently based on clock domains. The cross-clock domain crossing (CDC) signals present a special and difficult verification difficulty. The verification of clock domain crossings cannot be done using conventional functional simulation. Although correct clock domain implementation and verification have received little attention, static timing analysis (STA) is a crucial component of the timing confinement strategy. Conventional techniques offer an impromptu partial verification that is laborious, error-prone, and manual. Designs may contain functional flaws that are not discovered until the end of the design cycle or worse still, during post-silicon testing, if the sources of potential mistakes are not addressed and confirmed early on. At this point, correcting mistakes would be quite expensive. Chips are reportedly "dead in the water" in some large system households as a result of CDC issues.