有效位数
逐次逼近ADC
计算机科学
算法
校准
现场可编程门阵列
实现(概率)
最小均方滤波器
采样(信号处理)
电子工程
电容器
数学
自适应滤波器
计算机硬件
CMOS芯片
工程类
探测器
电气工程
电压
电信
统计
作者
Liu Wei,Gao Shangshang,Wang Xiao,Shang Shiguang
标识
DOI:10.1109/icicm54364.2021.9660322
摘要
In order to minimize the impact of SAR-ADC capacitance weight mismatch on conversion accuracy, a digital calibration algorithm applied to SAR-ADC is implemented based on sub-binary technology and perturbation technology. A Subradix-2 SAR-ADC model was established with Simulink. The LMS adaptive calibration algorithm was used to calibrate the output iteratively, and the algorithm was implemented on FPGA Xilinx Spartan-6 device. The results show that when the input signal frequency is 239.19kHz and the sampling frequency is 1MS/s, the ENOB is increased from 9.57 bit to 11.78bit.
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