记忆电阻器
MNIST数据库
冯·诺依曼建筑
神经形态工程学
计算机科学
人工神经网络
瓶颈
电网设计
记忆晶体管
晶体管
内存处理
拓扑(电路)
并行计算
炸薯条
电子工程
人工智能
嵌入式系统
电气工程
电阻随机存取存储器
搜索引擎
工程类
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操作系统
电压
电信
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作者
Can Li,Daniel Belkin,Yunning Li,Peng Yan,Miao Hu,Ning Ge,Hao Jiang,Eric Montgomery,Peng Lin,Zhongrui Wang,John Paul Strachan,Mark Barnell,Qing Wu,R. Stanley Williams,J. Joshua Yang,Qiangfei Xia
标识
DOI:10.1109/imw.2018.8388838
摘要
Memristors with tunable non-volatile resistance states offer the potential for in-memory computing that mitigates the von-Neumann bottleneck. We build a large scale memristor array by integrating a transistor array with Ta/HfO 2 memristors that have stable multilevel resistance states and linear IV characteristic. With off-chip peripheral driving circuits, the memristor chip is capable of high-precision analog computing and online learning. We demonstrate a weight-update scheme that provides linear and symmetric potentiation and depression with no more than two pulses for each cell. We train the array as a single-layer fully-connected feedforward neural network for the WDBC data base and achieve 98% classification accuracy. We further partition the array into a two-layer network, which achieves 91.71% classification accuracy for MNIST database experimentally. The system demonstrates high defect tolerance and excellent speed-energy efficiency.
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